EEPROM transistors have become increasingly popular for non-volatile memory applications, including data cards and logic applications where small amounts of memory might be needed for logic configuration or initialization. One of the problems in constructing EEPROMs, previously recognized by others, is that two layers of polysilicon are normally used, which increases process complexity and cost. A first layer is used for the floating gate. A second layer is used as the sense gate over the floating gate and for an adjacent select transistor. For example, see U.S. Pat. No. 4,833,096 to J. Y. Huang.
Others have previously constructed single layer EEPROM transistors to overcome the fabrication complexities of two polysilicon layers, for example, U.S. Pat. No. 4,807,003 to Mohammadi et al. Other patents showing similar structures are U.S. Pat. No. 4,823,316 to C. Riva and U.S. Pat. No. 4,935,790 to P. Cappelletti et al. The prior art recognized that a capacitive function served by the sense gate of a two-polysilicon layer EEPROM could be mimicked by a lateral capacitor constructed adjacent to an MOS transistor.
At first glance, it would appear that construction of a lateral capacitor would greatly increase chip size because a capacitor might be bigger than an EEPROM transistor and so a single layer EEPROM would have at least double the chip area of a two-layer polysilicon EEPROM transistor. However, an advantage of single layer poly EEPROM transistors over two-layer polysilicon EEPROM cells is less process complexity and cost in specific applications.
An object of the invention was to devise a more efficient single layer EEPROM transistor and cell using a low programming voltage.